JOB CATEGORY
EMPLOYMENT TYPE
Full-time, One-time
JOB LEVEL
Mid Career
YEARS OF EXPERIENCE
3-4 Years
LANGUAGE
English
Description
GIBIN P GEORGE
E-mail :[email protected]
Mobile : 974 30732199
974 55897055
Title: RTL Design & verification engineer
Technology Domain: 3 years and 6 months of experience in RTL design, verification, Simulation, Debugging and board level verification of the design.
Objective
To be an integral part of a respected and professional organization, where I can exploit myself and to contribute to the growth of organization.
Educational Qualification
Bachelor of Technology (B.Tech) in Electronics & Communications Engineering with first class from LBS College of Engineering, Kasaragod, Kerala during 2004-08.
Brief on Skill Set –
- RTL hardware design using VHDL and Verilog.
- Basics of RTL verification using UVM & System verilog.
- Simulation of the design modules using ModelSim.
- Synthesizing the RTL modules using Xilinx/Altera tools.
- Board level verification of the design.
HDL/HVL
VHDL, Verilog, System verilog
Telecom experience
BTS Installation
Verification methodology
UVM
Development Tools
Xilinx ISE, Altera Quartus II
Simulation Tools
ModelSim, QuestaSim
Test and Debugging Tools
Chipscope Pro Analyzer, Oscilloscope
Interfacings
AMBA AXI, AHB, APB, MIL-STD 1553, I2C bus
Operating Systems
Windows XP/9X/NT/2000, Linux
Other tools
Microsoft Office Suite
Nature of job done
- Analyzing the requirement from client companies.
- Prepare the architecture and the schedule for the project
- Write the RTL for the modules assigned and integrate the modules.
- Simulate the design at various levels.
- Verify the design on the board.
- Prepare detailed document for the project.
Experience Summery
1) Previous employer : Mindteck (India) Ltd.
Designation : Hardware Design engineer (FPGA)
Department : EDS Hardware Services
Period : May 2012 – June 2013, Aug 2013 – Oct 2013(Contract basis)
Location : Bangalore, India
Designed, implemented and tested I2C master, slave, ADC and DAC interfaces.
2) Previous employer : Digeratti Systems
Designation : Design engineer(FPGA)
Period : Mar 2010 – May 2012
Location : Bangalore
Designed, implemented and verified MIL-STD_1553B bus interface module on Spartan-3 FPGA, that provides a complete integrated interface between a host processor and MIL-STD-1553 bus.
Training program
Institute : Maven Silicon.
Corse title : VLSI Verification
Period : Oct. 2013 – Jan.2014(Training) & March 2014 – June2014(Internship)
Role : Trainee
Location : Bangalore, India
Completed an advanced training program in ASIC verification using system verilog and UVM methodology. Designed RTL for AHB to APB bridge and verified it using UVM. Verified AXI protocol.
Verification Project Details
1) AHB to APB bridge
Organization : Maven Silicon
Team size : 02
AHB to APB bridge RTL is designed and verified for single master multiple slaves. The bridge is an AHB slave providing interface between AHB and APB. Read and write transfers on the AHB are converted to equivalent transfers on APB. Wait states are added during transfers to and from APB when AHB is required to wait.
Role Played: Designed, developed the RTL and verified it using UVM.
2) AXI protocol verification
Organization : Maven Silicon
Team size : 02
AXI protocol is verified for single master single slave. The AXI master and slave modules were created in test bench to ensure that the communication takes place properly as per specification. For master write, Narrow, Aligned, Unaligned transactions were verified for various burst size and burst length. For master read, burst and overlapping burst transfers were verified.
Role Played: Designed, developed the RTL and verified it using UVM.
RTL Design Project Details
1) MIL-STD-1553 Bus Interface
Client organization : A public sector customer from defense applications domain
Team size : 03
Mil-Std-1553B protocol data bus interface being implemented on SPARTAN-3 FPGA that provides a complete integrated interface between a host processor and MIL-STD-1553 bus. The system uses command/response method. It interfaces a host processor to the external RAM while minimizing the board space.
The MIL-STD-1553B interface incorporates processor interface, memory management and MIL-STD-1553B protocol elements such as Bus Controller, Remote Terminal, and Bus Monitor.
Role Played: RTL development and on board testing of the modules.
2) I2C Slave Module
Client organization : USA customer from embedded computing domain
Team size : 03
The I2C slave module is implemented on Max II CPLD from Altera. It can work at 100 KHz and 400 KHz clock frequency. It supports features like burst read and write operation. Debounce logic is incorporated to avoid any chance of interpreting invalid glitches as data.
A Watch Dog Timer with programmable range is implemented with the help of a 22 bit counter. The module is capable of handling USB over current.
Role Played: RTL development and on board testing of the I2C slave module.
3) I2C Master core
Client organization : USA customer from embedded computing domain
Team size : 03
The I2C master core incorporates all features required by the v.2.1 of I2C specification including arbitration, multi-master systems and High-speed transmission mode. It can operate from a wide range of the clock frequencies.
The I2C core can be configured as a master transmitter or master receiver. It uses 16 bit address and data interface to the host. This core is having an internal register set of 10 configuration registers and 256 data registers.
Role Played: File I/O based test bench development and verification of the complete I2C Master core.
4) ADC & DAC Interfaces
Client organization : USA customer from embedded computing domain
Team size : 03
ADC and DAC is configured using internal registers in CPLD, which are loaded with configuration data by the processor. ADC input mux selection logic is incorporated for channel selection. For ADC testing, converted data from ADC is read and is compared with its input channel voltage. For DAC testing, the DAC output is converted to digital data with ADC and is compared with DAC input register value.
Role Played: RTL development and on board testing of ADC and DAC interfaces.
Personal Details
Date of Birth : 18/05/1986
Gender : Male
Marital Status : Single
Languages Known : English, Hindi and Malayalam.
Nationality : Indian
Address : box no 24551,
Doha, Qatar
Place : Doha
Date : GIBIN P GEORGE
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